The present invention relates to a semiconductor integrated circuit using nonvolatile memory cells to store control information for defect relief, trimming of circuit characteristics or function switching with respect to a plurality of circuit modules, and a method of manufacturing a semiconductor integrated circuit with control information written into such nonvolatile memory cells. The present invention relates to, for example, a technology effective for application to a microcomputer or a system LSI equipped with a logic circuit and a RAM.
A technology for causing a nonvolatile memory cell like a flash memory cell to hold relief information or the like used for defect relief of an on-chip memory and a characteristic adjustment to a logic circuit has been described in Unexamined Patent Publication No. 2000-149588 (corresponding U.S. Pat. No. 2002/163840). According to it, relief information or the like for a defect of a RAM is stored in the flash memory in a semiconductor integrated circuit in which the RAM and the flash memory are implemented on a chip together with a CPU (Central Processing Unit). Further, the relief information or the like held in the flash memory is read into a general-purpose bus as part of an initializing operation at power-on or the like, and the read relief information or the like is loaded into a register inherent in the RAM or the like. The relief information or the like loaded into the register is supplied to a defective address determination circuit, a switching circuit for switching a defective address to a relief address, etc., in the corresponding RAM.
The present inventors have discussed control information for defect relief, trimming of circuit characteristics or function switching with respect to on-chip circuit modules.
Firstly, high reliability is required of the storage of such control information. When an error occurs in such control information even if only slightly, each circuit module causes a malfunction on a permanent basis or causes an undesired reduction in performance. When a flash memory used on a general-purpose basis upon an actual operation of an LSI is used in the retention of the control information at this time, reliability similar to reliability for general data can be merely obtained for the control information.
Secondly, when control information is initially set using a general-purpose bus, there is a need to provide a switching circuit for changing a configuration of connection of the general-purpose bus used even in an actual operation and each circuit module or a connecting destination in each circuit module, and control logic thereof. Moreover, control on the selection of a register corresponding to a destination to be loaded, addressing and the like is required to load control information into each circuit module by use of a common bus. In brief, a circuit configuration becomes relatively complex.
Thirdly, there is a need to avoid easy rewriting of such control information. Accordingly, address management of a system is also needed in such a manner that rewriting of the control information can be effected on the control information storage region of a flash memory available upon an actual operation in a privileged mode or a user nondisclosure mode alone.
Fourthly, if there is a need to write control information into the flash memory in each case when the confirmation of operation by control information is performed, the frequency of rewriting increases due to the operation confirmation, and hence there is a possibility that characteristic deterioration is incurred in each nonvolatile memory cell.
An object of the present invention is to provide a semiconductor integrated circuit capable of assuring high reliability with respect to control information delivered for defect relief, trimming of circuit characteristics or function switching for a plurality of on-chip circuit modules.
Another object of the present invention is to provide a semiconductor integrated circuit capable of simplifying a circuit configuration necessary for delivery of control information for defect relief, trimming of circuit characteristics or function switching.
A further object of the present invention is to provide a semiconductor integrated circuit which lessens a possibility that a rewrite operation will be undesirably effected on control information for defect relief, trimming of circuit characteristics or function switching.
A still further object of the present invention is to provide a semiconductor integrated circuit capable of reducing to a minimum, the frequency of rewriting of each nonvolatile memory cell in order to perform operation confirmation by control information for defect relief, trimming of circuit characteristics or function switching.
A still further object of the present invention is to provide a method of manufacturing a semiconductor integrated circuit, which enhances reliability of an operation based on control information for defect relief, trimming of circuit characteristics or function switching.
The above, other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
Summaries of typical ones of the inventions disclosed in the present application will be described in brief as follows:
[1] A semiconductor integrated circuit according to the present invention has a plurality of circuit modules connected to a first wiring such as a common bus or the like and includes a fuse circuit which has a plurality of nonvolatile memory cells respectively storing control information for defect relief, trimming of circuit characteristics or function switching with respect to the plurality of circuit modules and which allows memory information to be electrically read therefrom. A plurality of volatile register circuits provided with a plurality of volatile memory cells to store the control information therein are adopted in association with the plurality of circuit modules every the plurality of circuit modules. The fuse circuit and the plurality of register circuits are connected by a dedicated second wiring for the purpose of transfer of the control information. A control circuit is provided which controls application of an operating voltage to each of the nonvolatile memory cells to enable reading of memory information from the fuse circuit, controls the transfer of the control information read from the fuse circuit to each of the register circuits through the second wiring, and performs control for releasing application of the operating voltage to each of the nonvolatile memory cells after reading of the control information from the fuse circuit to the second wiring.
In a further detailed one aspect of a semiconductor integrated circuit according to the present invention, a first register circuit is provided which includes a plurality of volatile memory cells for holding the control information read from the fuse circuit. The first register circuit and a plurality of second register circuits are respectively connected by the second wiring dedicated for the transfer of the control information. At this time, a control circuit performs control on application of a voltage enabling reading of the memory information from each of the nonvolatile memory cells of the fuse circuit to the nonvolatile memory cell, control on the transfer of the control information read from the nonvolatile memory cells to the first register circuit to the second register circuits through the second wiring, and control for releasing the application of the voltage enabling the reading of the memory information from the nonvolatile memory cells to the nonvolatile memory cells after the reading of the control information into the first register circuit.
According to the above means, each nonvolatile memory cell of the fuse circuit unsharing the first wiring like the common bus is used to store control information. Thus, it is possible to suppress deterioration in the reliability of storage of the control information, which is in danger of its manifestation where a flash memory intended for general purpose use is used to store the control information. In brief, nonvolatile memory cells each having reliability higher than reliability of information storage, which is ensured by the general-purpose memory, can be utilized.
Since the second wiring used to transfer the control information is a wiring dedicated therefor, it needs not perform switching between connections to circuit portions used for actual operations in the circuit modules and their control. Consequently, a circuit configuration for delivering the control information can be simplified.
Since the application of the operating voltage to each of the nonvolatile memory cells is released after reading of the control information from the fuse circuit to the register circuits (second register circuits), no electrical stress is applied to each of the nonvolatile memory cells of the fuse circuit even if an actual operating period of the semiconductor integrated circuit exists subsequently to its release. Even in such a viewpoint, the reliability of storage of the control information is enhanced.
As one preferable form of the present invention, the fuse circuit may be placed in one location of the semiconductor substrate. A high-voltage operated circuit necessary to write memory information can be concentratedly placed in one location, and a space used to make separation from a low-withstand circuit portion or to be away therefrom can be held to a minimum.
As one preferable form of the present invention, the operation of the control circuit may be started in response to an instruction for initializing the semiconductor integrated circuit. It is rational to perform the defect relief, the trimming of the circuit characteristics or the function switching for each circuit module immediately before an actual operation is started. In the case of a microcomputer, for example, it may be performed in accordance with power-on reset or system reset.
As one preferable form of the present invention, the individual register circuits may be series-connected to the circuit modules by the second wiring. Sequentially transmitting control information on a serial basis according to clock-synchronized shift register operations enables delivery of the control information to the plurality of register circuits. Described more specifically, the first register circuit is a shift register which holds control information parallel-outputted from the fuse circuit and outputs the same on a serial basis. The second register circuits are shift registers which have serial input terminals connected upstream of the second wiring, serial output terminals connected downstream of the second wiring, and parallel output terminals connected to their corresponding circuit modules.
As one preferable form of the present invention, testing external interface means may be provided which makes it possible to output information on the second wiring to the outside of the semiconductor substrate and to input data from outside to the second wiring. Testing control information inputted from outside can be directly loaded into its corresponding register circuit. The frequency of rewriting each nonvolatile memory cell to execute operation confirmation by control information for defect relief, trimming of circuit characteristics or function switching can be reduced to the utmost. Consequently, the possibility of deterioration of characteristics of each nonvolatile memory cell can be reduced.
As one preferable form of the present invention, the fuse circuit has a nonvolatile memory cell assigned for storage of a sign bit indicative of whether writing of control information into each of the nonvolatile memory cells has been done. The presence or absence of write completion of the control information can be easily recognized. It is possible to prevent deterioration of device characteristics and instability of information storage due to incorrect overwriting before they happen.
The control information stored in the fuse circuit may be used as any one of information for substituting a defective circuit module with a spare circuit module and control information for relieving a partial defect in each circuit module, or both information. Using the control information as both information provides convenience where the defect relief is hierarchically effected on the circuit modules. A method of substituting a circuit module with a spare circuit module is used when circuit modules constituting circuit functional units are arranged in plural form to constitute a functional unit.
[2] As one preferable form of the present invention, such a structure that upon a read operation, a channel current may not be passed or fed through each nonvolatile memory element and a large word line voltage may not be applied thereto, is adopted in each of the nonvolatile memory cell to thereby prevent the occurrence of inversion of data due to charge gain or the like. Namely, each of the nonvolatile memory cells may preferably include nonvolatile memory elements having first source electrodes, first drain electrodes, floating gate electrodes and control gate electrodes and capable of having different threshold voltages, read transistor elements having second source electrodes and second drain electrodes, having the floating gate electrodes as gate electrodes and capable of having mutual conductances (or switch states) different according to threshold voltages held by the nonvolatile memory elements, and a selection transistor which connects the read transistor elements to a read signal line.
For instance, when one threshold voltage of each of the nonvolatile memory elements is set to a relatively high threshold voltage (corresponding to a threshold voltage in a write state in which electrons are injected into a floating gate thereof), and the other threshold voltage is set to a low threshold voltage (corresponding to a threshold voltage in an erase state in which electrons are emitted from the floating gate2), each of the transistor elements is brought to a cutoff state in a high threshold voltage state and brought to an on state in a low threshold voltage state (its reverse might occur depending on conductivity type of each transistor element). The erase state of each nonvolatile memory element can be achieved by, for example, setting the first drain electrode and control gate electrode of the nonvolatile memory element to 0V like a circuit ground voltage, setting the first source electrode of the nonvolatile memory element to 6V and pulling out or drawing electrons from the floating gate electrode to the first source electrode by a tunnel current. The write state can be achieved by, for example, setting the first drain electrode and control gate electrode of each nonvolatile memory element to 5V, setting the first source electrode of the nonvolatile memory element to 0V like the circuit ground voltage, and injecting hot electrons generated at the first drain electrode into the floating gate.
Since the floating gate electrodes of the nonvolatile memory elements serve as the gate electrodes of the read transistor elements, the read transistor elements respectively take or assume switch states or mutual conductances corresponding to electron-injected states/electron-emitted states of the floating gate electrodes, in other words, write states/erase states. Thus, even if a select level is not applied to the control gates, a current corresponding to the switch states or the mutual conductance states can be passed or fed through the transmission means. Since no select level is applied to the control gate electrodes, depletion type MOS transistors may be adopted for the read transistor elements in terms of ensuring of the necessary amount of read signal.
On the other hand, when enhancement type MOS transistors are adopted for the read transistor elements, the select level may preferably be supplied to each control gate electrode even upon a read operation in terms of ensuring of the necessary amount of read signal. It can be also understood from such a format that the read transistor elements respectively have threshold voltages different according to the electron-injected states/electron-emitted states of the floating gate electrodes, in other words, write states/erase states.
From the above, there is no need to cause a channel current to flow through each of the nonvolatile memory elements according to the threshold voltage upon the read operation. Upon the read operation, the source electrodes and drain electrodes of the nonvolatile memory elements may be respectively set to a circuit ground potential like 0V. Thus, the injection of weak hot electrons from the first drain electrodes to the floating gates does not occur. When the control gate electrodes are also set to the circuit ground potential at this time, no tunnel current occurs either. Even if the select level is applied to each control gate electrode, no tunnel current occurs between the first drain electrode and the floating gate electrode. While a weak tunnel or the like might occur between the second drain electrodes of the read transistor elements, this is considered to present no problem if the select level of each control gate electrode is low. Thus, a problem associated with the inversion of data due to charge gain does not occur upon the read operation. Consequently, the performance of retaining data over a long period is enhanced and hence a reduction in read defective rate or fraction can be realized.
Each of the nonvolatile memory elements has a MOS capacitive element in which a capacitance electrode is provided over a first semiconductor region functioning as a control gate electrode with an insulating layer interposed therebetween, and a MOS transistor having a first source electrode, a first drain electrode and a gate electrode formed in a second semiconductor region. The capacitance electrode may adopt such a configuration as to be commonly connected to the gate electrode and function as a floating gate electrode.
[3] In order to further take data retention measures against each information memory cell subjected to charge gain measures by a pair structure of the nonvolatile memory elements and read transistor elements to thereby improve a read defective rate or fraction, the following configurations may be adopted.
Firstly, the nonvolatile memory elements and read transistor elements are respectively provided in pairs, and one read transistor element shares a floating gate electrode of one nonvolatile memory element, whereas the other read transistor element shares a floating gate electrode of the other nonvolatile memory element, and the pair of read transistor elements is series-connected to the selection transistor element. In such a configuration, the pair of nonvolatile memory elements is both programmed into a write state or an erase state. In the write states of both the nonvolatile memory elements, both the read transistor elements are respectively held in an off state. While the possibility that electrical charges held in the nonvolatile memory elements kept in the write state will leak therefrom due to some reasons, is not 0 at random, a serial path of the read transistor elements remains in a cutoff state even if the electrical charge held in one nonvolatile memory element leaks therefrom. The probability that the electrical charges retained in both the nonvolatile memory elements will leak therefrom, is extremely low. Consequently, data retention is improved and hence a read defective rate or fraction can be further reduced.
Secondly, the nonvolatile memory elements and read transistor elements are respectively provided in pairs, and one read transistor element shares a floating gate electrode of one nonvolatile memory element, whereas the other read transistor element shares a floating gate electrode of the other nonvolatile memory element, and the pair of read transistor elements is parallel-connected to the selection transistor element. In a manner similar to the above even in such a configuration, the pair of nonvolatile memory elements is both programmed into a write state or an erase state. Since the second example is placed on the assumption that the read transistor elements are different in conductivity type from the above, both the read transistor elements are held in an on state when the nonvolatile memory elements are respectively brought to the write state. While, at this time, the possibility that electrical charges retained in the nonvolatile memory elements held in the write state will leak therefrom due to some reasons, is not 0 at random, a parallel path of the read transistor elements remains in an on state even if the retained charge leaks from one of the nonvolatile memory elements. The probability that the electrical charges retained in both the nonvolatile memory elements will leak therefrom, is extremely low. Consequently, data retention is improved and hence a read defective rate or fraction can be further reduced.
[4] A method of manufacturing a semiconductor integrated circuit, according to the present invention, including a plurality of circuit modules, a fuse circuit which has a plurality of nonvolatile memory cells capable of writing therein control information for defect relief, trimming of circuit characteristics or function switching with respect to the plurality of circuit modules and which allows memory information to be electrically read therefrom, a dedicated wiring which allows the memory information of the fuse circuit to be delivered to the circuit modules, and testing external interface means which makes it possible to output information on the dedicated wiring to the outside of a semiconductor substrate and to externally input data to the dedicated wiring, comprises a first process for supplying control information from the testing external interface means to each of the circuit modules through the dedicated wiring, a second process for confirming an operation of each of the circuit modules in a supplied state of the control information, and a third process for writing control data in the fuse circuit according to the result of confirmation by the second process.
From the above, there is no need to write the control information in each nonvolatile memory cell on a case-by-case basis when the operation is confirmed based on the control information. Therefore, it is not necessary to rewrite each nonvolatile memory cell for the purpose of the operation confirmation. Consequently, the possibility that each nonvolatile memory cell will incur deterioration of characteristics thereof, is reduced.